1. Field of the Invention
The present invention generally relates to wiring systems for multi-chip modules (MCM) and, more particularly, to wiring systems which facilitate repair and engineering changes in multi-chip modules fabricated from a plurality of layers, such as multi-layer ceramic modules and module wiring formed by thin film techniques.
2. Description of the Prior Art
The formation of integrated circuit chips in accordance with different technologies has been known for a number of years. A demand for increased complexity of electronic systems including such integrated circuit chips has caused the development of multi-chip modules including a plurality of integrated circuit chips. Such modules are necessary when the desired circuitry must be integrated on chips by such differing technologies that formation on a single chip is impossible or economically disadvantageous or where the circuit complexity and device counts are too large to be integrated on a single chip consistent with good chip production yields.
Such multi-chip modules (MCM) usually take the form of relatively large, multi-layer constructions having a surface on which a plurality of chips may be mounted. The multi-layer construction is similar to multi-layer circuit boards in that wiring can be run in a direction parallel to the surface at the interface between any two layers. Wiring can be run perpendicular to the surface and between wiring layers with through-holes or "vias" in the layers which are selectively filled with conductive materials. Multi-chip modules have been implemented with a variety of technologies including multi-layered co-fired ceramics, silicon based thin film structures, ceramic based thin film structures and combinations of those techniques.
However, because of the multi-layer construction, there is no access to wiring other than on the surface of the multi-layer structure. Therefore, engineering changes cannot readily be made. Perhaps of equal importance is the fact that while electronic modules are large relative to the chips they contain, they are often very complex and of fairly small overall dimensions. Therefore, they are subject to connector defects in the same manner as the chips to be mounted thereon and manufacturing yields of the multi-layer structure must also be considered. The length of the conductors is quite substantial because complex wiring metallization must be provided to allow each output terminal of one chip to be connected to a plurality of other input terminals on other chips. Additionally, so-called fan-out wiring is often provided to interface between the fine wiring patterns characteristic of the connector spacing of the chips and the relatively more coarse wiring patterns on the MCM. The problem of circuit defects is aggravated by the manufacturing processes used to create the multi-layer structures which, for co-fired ceramic technology, involve spreading of a conductive paste with a nozzle through a fine stencil, both of which are subject to wear and scoring, and the lifting off of the paste where conductors are not desired. Either insufficient or irregular spreading of the conductive paste or the lifting off of small portions of the stencilled pattern may cause undesired conductor defects within the multi-layer structure.
Since such structures are complex and require a number of processing steps for each layer, substantial expense is involved in fabrication of the multi-layer structure. It is therefore economically important that the multi-layer structures be repairable. It is similarly important that engineering design changes be possible. In the past, this has been accomplished by a process known as "ECing", or the implementing of engineering changes, which required providing one or more layers of redistribution wiring from the chip I/O pads to EC pads on the top surface of the Multi-layer structure. The signal connection is then made by wiring from EC pad to EC pad and by redistribution wiring formed in the multi-layer structure from EC pad to chip I/O pad. However, these layers of redistribution wiring are also subject to the same potential defects as other wiring layers and are not repairable. Further, such patterns of redistribution wiring are in close proximity to each other, requiring high line (e.g. wiring pattern) quality, and a parasitic capacitance will exist causing signal delays, reduced noise margins, and other effects, thereby posing a severe restriction on wiring design rules. Additionally, to function for facilitating a wide variety of repair and engineering changes, hereinafter referred to collectively as engineering changes (EC), a significant amount of product and process complexity is required. This function also traditionally requires additional area for the redistribution wiring and EC pads, thus limiting the maximum possible density of the MCM. This, of course, also limits the performance of the MCM both operationally, from the number of ICs which can be included, and functionally due to delays, noise, etc., associated with longer wiring and parasitic capacitances.
Using previous technology, as shown in FIG. 6, a repair or engineering change is made by point-to-point wiring with a so-called "yellow wire" 110. To make an added connection, an end of the yellow wire was connected (e.g. bonded) to an EC pad 105 and the wire routed to another EC pad 111' where the other end was connected. A portion of the originally formed signal net 107, which may have been defective (e.g. at 108), is deleted by deleting the original connectors 106 from the EC pads to the signal pads 111. Performing such an operation on a small area of a module requires substantial complexity of automation, particularly where the connections are made for purposes of repairs and will change from module to module and must be combined with automated testing of the extremely complex circuits which are formed.
It should be noted from FIG. 6 that the connection from chip 101 to the EC pad 105 includes a pad 102, often referred to as a C4 pad, a via connection 103 below the EC pad, another via connection to the redistribution wiring layer 104 and similar connections to bring the connection back to the surface of the substrate. A defect 109 can occur at any point along this connection and such a defect is not repairable. It should be further noted from FIG. 6 that repair of defect 108 would normally be done from EC pad 105 to EC pad 105', removing both delete lines 106 and 106'. However, because a portion 112 of the signal net 107 remains intact, the "yellow wire" connection 110 can be made to either EC pad 105' or signal capture pad 111' but the delete line 106' must not be removed. Therefore, only the portion of the defective wiring between signal capture pad 111 and defect 108 can be removed from the circuit by removal of delete line 106 to reduce parasitic capacitance. Portion 107', which is non-functional because of defect 108 remains connected to the circuit and contributes to the parasitic capacitance. The same would be true of redistribution wiring 104 even if a repair could be accomplished since there is no way to remove any portion of the connection between the C4 pad 102 and EC pad 105 from the circuit.
As examples of other prior art wiring schemes which allow some degree of repairs and engineering changes to be made, U.S. Pat. No. 4,489,364 to Chance et al shows an electronic circuit module in which connections to pads to which chips are connected are buried within the body of the multi-layer structure but are periodically brought to the surface of the module and linked by EC pads of a so-called "dog-bone" shape. Continuity of these connections may be broken by severing the narrow portion of the dog-bone and EC connections may be made thereto either with or without severing the original connection. However, if a defect occurs in or between the C4 pad and the first EC pad, no repair is possible and the module must be discarded. The wiring through via holes is particularly vulnerable to the occurrence of discontinuities, as well, which may or may not be repairable and, in any event, repair would require point-to-point wiring over a considerable distance, further increasing parasitic capacitance of the overall wiring system. It can also be readily appreciated that the length of wiring involved in this scheme, including the repeated vertical traversals of the multi-layer structure through vias, is large and has a large lumped capacitance.
Additionally, U.S. Pat. No. 4,746,815 to Bhatia et al provides a switching circuit within the module to allow sharing of EC pads between receiver and driver circuits. U.S. Pat. No. 4,652,974 to Ryan, particularly at FIGS. 1 and 6, shows the complexity of the prior art redistribution wiring layers. U.S. Pat. No. 4,453,176 to Chance et al shows wiring to capacitances buried within the multi-layer structure. U.S. Pat. No. 4,840,924 to Kinbara shows a particular structure for the dog-bone EC pads. U.S. Pat. No. 4,254,445 to Ho shows a staggered chip location arrangement for a large number of chips in a module to minimize potential wiring cross-overs and maximize the number of EC pads which can be provided. U.S. Patent to Ecker et al shows a repairable multi-level overlay system using redistribution. U.S. Pat. No. 4,546,413 to Feinberg et al shows a module structure in which EC pads are provided on both major surfaces of the multi-layer structure. U.S. Pat. No. 4,706,165 to Takenaka et al shows a multi-layer structure in which connections to module connection pins are made through vias to EC pads at the upper surface of the module to increase the types of engineering changes and repairs which can be made.